1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a MOS (metal oxide semiconductor) field effect transistor having an LDD (lightly doped drain) structure and a method of manufacturing the same, for suppressing a hot carrier effect by reducing peak field strength of a drain depletion layer which is caused in a pinch-off state.
2. Description of the Background Art
A MOS field effect transistor is basically formed by providing a metal electrode on an Si substrate with a thin oxide film interposed therebetween for defining the so-called MOS capacitor, and arranging a source for serving as a carrier source and a drain for extracting carriers on both sides of the MOS capacitor. The metal electrode provided on the oxide film, which is adapted to control conductance between the source and the drain, is called a gate electrode. Such a gate electrode is generally prepared from a polysilicon material which is doped with impurity ions, or a metal silicide material which is formed by heat treating a metal having a high melting point, such as tungsten, deposited on a polysilicon material in inert gas.
When the voltage (gate voltage) of the gate electrode is lower than a threshold voltage V.sub.th which is necessary for inverting the conductivity type of a portion (channel) close to a surface portion of the Si substrate between the source and the drain, no current flows since the source and the drain are isolated from each other by a p-n junction. When a gate voltage exceeding the threshold voltage V.sub.th is applied, the conductivity type of the channel surface is inverted to define a layer of the same conductivity type as the source and the drain in this portion, whereby a current flows across the source and the drain.
If distributions of impurity concentration are abruptly changed in the boundaries between the source, the drain and the channel, levels of field strength are increased in these portions. The carriers attain energy by such electric fields, to cause the so-called hot carriers. Such carriers are injected into the gate insulating film, to define interfacial levels at the interface between the gate insulating film and the semiconductor substrate, or be trapped in the gate insulating film. Thus, the threshold voltage and transconductance of the MOS transistor are deteriorated during the operation. This is the deterioration phenomenon of the MOS transistor caused by the hot carriers. Further, the so-called avalanche resistance against source-to-drain avalanche breakdown is also deteriorated by the hot carriers. The MOS-LDD field effect transistor is adapted to relax the field strength by reducing n-type impurity concentration in the vicinity of the source and the drain and loosening the change of concentration distributions, thereby suppressing deterioration of the MOS transistor caused by hot carriers and improving source-to-drain avalanche resistance.
A conventional MOS-LDD field effect transistor is manufactured by a method shown in FIGS. 1A to 1F, for example. According to this method, a gate insulating film 3 is formed by the so-called LOCOS method on an element forming region of a p-type semiconductor substrate 1 which is enclosed by an element isolation film 2 (FIG. 1A). Then, p-type impurity ions such as boron ions are implanted into the overall surface of the semiconductor substrate 1 for controlling a threshold voltage, to form an ion-implanted region 4 (FIG. 1B). Thereafter a polysilicon film is deposited on the overall surface of the gate insulating film 3 by a low pressure CVD process, to form a gate electrode 5 through photolithography and reactive ion etching (FIG. 1C). In place of the polysilicon film, the gate electrode 5 may be formed by a two-layer film of a metal having a high melting point such as tungsten, molybdenum or titanium, or a silicide thereof, and polysilicon. This gate electrode 5 is doped with phosphorus ions, for example, for improvement in conductivity.
Then, n-type impurity ions such as phosphorus ions or arsenic ions are vertically implanted into the surface of the semiconductor substrate 1 through the gate electrode 5, serving as a mask, to form n-type ion-implanted layers 6 (FIG. 1D). Thereafter an insulating film of silicon dioxide or the like is deposited on the overall surface of the semiconductor substrate 1 by a low pressure or normal pressure CVD process, and anisotropic etching is performed to form side wall spacers 7 (FIG. 1E). Then, n-type impurity ions such as phosphorus ions or arsenic ions are vertically applied to the surface of the semiconductor substrate 1, the gate electrode 5 and the side wall spacers 7, serving as masks, to form n-type implanted layers 8 which are higher in concentration than the ion-implanted layers 6 (FIG. 1F). Thereafter heat treatment is performed for activating the implanted impurity ions, thereby completing the MOS-LDD field effect transistor.
Although a p-type semiconductor substrate is employed in the aforementioned prior art, the substrate may be provided with a p-type well, in which p-type impurity ions are implanted, at least in the vicinity of its surface. Further, the substrate may be formed by an n-type semiconductor substrate, or a substrate provided with an n-type well, in which n-type impurity ions are implanted, at least in the vicinity of its surface. In this case, the gate electrode 5 is of the p-type, and p-type ion-implanted layers 6 and 8 are formed in the source and drain regions.
According to the MOS-LDD field effect transistor obtained by the aforementioned conventional method, the change in distribution of impurity concentration is relaxed in the source and drain regions since the ion-implanted regions 6 of lower concentration are provided on the sides of the source and drain regions adjacent to the channels. Thus, field strength levels are reduced in these portions, to prevent the transistor from the deterioration caused by the hot carriers.
In the conventional MOS-LDD structure, however, the low-concentration impurity diffusion layers (ion-implanted layers 6) of the source and drain regions are diffused laterally toward a portion under the gate electrode 5 upon high-temperature heat treatment in a later step. Thus, parasitic capacitance is added between the gate electrode 5 and the source and drain regions, thereby reducing the operating speed an integrated circuit and hindering refinement of the transistor.
A similar problem is caused in a complementary MOS integrated circuit, for example, which is provided with both n-channel and p-channel field effect transistors, when LDD structures are formed by the aforementioned conventional method. Since diffusion coefficients of impurity elements which are implanted into source and drain regions are varied with types thereof, the optimum width of a side wall spacer for the first conductivity type channel is not necessarily suitable for the region of the second conductivity type channel.
Also in the case of field effect transistors having the same conductivity type of channels, it is impossible to attain optimum widths of side wall spacers required for the respective transistors when concentration profiles of impurity diffusion layers of source and drain regions must be changed in response to performance required therefor.
Japanese Patent Laying-Open No. 61-5571 (1986), 63-226055 (1988) or 63-246865 (1988) discloses a conventional manufacturing method for solving the aforementioned problem. The manufacturing method described in such a gazette is adapted to separately form side wall spacers of n-channel and p-channel MOS transistors, which are provided on the same semiconductor substrate. Namely, when the side wall spacer for the first conductivity type channel is formed, an active region of the second conductivity type channel is covered with a resist film.
A typical example of such a conventional manufacture method is shown in FIGS. 2A through 2H. In this manufacture process, a gate electrode 5 is first formed on respective surfaces of a p-type region and n-type region of a semiconductor substrate 1, which are isolated from each other by an element isolation film 2, with a gate insulating film 3 interposed between the gate electrode 5 and the respective surfaces of the p-type and n-type regions. A silicon nitride film 9a is then deposited on the overall surface of the semiconductor substrate 1 (FIG. 2A). Only the nitride silicon film on the n-type region is thereafter covered with a resist mask (not shown), to remove only the silicon nitride film 9a formed on the p-type region. After the resist mask on the n-type region is removed (FIG. 2B), an insulating film 7a is deposited on the overall surface of the semiconductor substrate 1 (FIG. 2C). Then, the insulating film 7a is subjected to a reactive ion etching, thereby to form side wall spacers 7b and 7c (FIG. 2D). The silicon nitride film 9a formed on the n-type region and the side wall spacer 7c are then removed (FIG. 2E). After that, only the portion on the p-type region is covered with a silicon nitride film 9b. An insulating film 7d is again deposited on the overall surface of the semiconductor substrate 1 (FIG. 2F) with the portion on the p-type region covered with the silicon nitride film 2b. This insulating film 7d is thereafter subjected to the reactive ion etching, so as to form side wall spacers 7e and 7f (FIG. 2G). Then, the silicon nitride film 9b formed on the p-type region and the side wall spacer 7e are removed, so that the side wall spacers 7b and 7f are formed on the p-type region and the n-type region, respectively. According to the technique described in the above gazette, it is possible to make the widths of the side wall spacers for the p-type and n-type channels different from each other at need. However, although the resist film can be formed through a single step for each conductivity type channel region, CVD processors for forming all side wall spacers require long times since only those for the channel region of one conductivity type are formed in a single CVD process. This leads to a problem since the CVD processing time is relatively long as compared with formation of the resist film (FIG. 2H).